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NESL
| Young H Cho | |||||
| BIOGRAPHY | ||||||
| Young Cho graduated from UC Berkeley with a bachelors degree in Computer Science. While attending Berkeley, he was in a research project group called NOW ,Networks of Workstations. From July of 1996 to August of 1999 he worked as an engineer/programmer at Myricom, Inc. Myricom is the main network interconnect technology provider for the majority of the fastest clustered computers in the world. He took a leave of absence from Myricom after three years to return to academia. He began his Masters program in Computer Engineering at UT Austin in Fall of 1999. By Spring of 2001, he completed his Masters of Science in Engineering from Electrical Computer Engineering department while working for UT Research Laboratory Applied Research Laboratory in the University of Texas at Austin. Then he moved to Los Angeles to attend University of California, Los Angeles for the doctorate degree in Electrical Engineering under his advisor William Mangione-Smith. In June of 2005, he completed his Ph.D. on the dissertation topic of Advanced Computer Network Security. He then came to Washington University in St. Louis as a Visiting Assistant Professor in Computer Science Engineering department. On July of 2007, he leveraged all of his prior expertise to independently start a technology company, Open Acceleration Systems Research, specializing research and development of various high-performance applications using commodity-off-the-shelf (COTS) components. He is also a post-doctorol scholar at Networked & Embedded Systems Laboratory (NESL)of UCLA. | ||||||
| RESEARCH INTERESTS | ||||||
| Young Cho has background in the areas of embedded systems, computer architecture, and computer networks. His recently research includes high-performance image compression, high-performance IPSec accelerators, dynamic thermal feedback control and accurate benchmarking of modern processors, and sensor network localization and time synchronizations. | ||||||
| EDUCATION | ||||||
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BA
in Computer Sciences, UC Berkeley, 1996
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| PROFESSIONAL EXPERIENCE | ||||||
| - 17 years experience in formal procedural/object oriented programming languages - 13 years experience in logic to system level computer architecture designs and instruction - Thorough understanding of FPGA and ASIC design languages and methodologies - Proficient in co-designing systems using both software and hardware - Successful development of commercial products using state-of-the-art technologies - Demonstrated management skills through leading successful research teams and teaching - Extensive experience in research and development of emerging technologies - Long term vision for technical trend to anticipate and plan for the future goals - Extensive list of publications in competitive technology conferences, journals, and books - Ability to write successful research and development grant proposals - Demonstrated analytical, investigative and problem-solving capabilities - Team-oriented with superior communication and project management skills |
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| PROFESSIONAL SERVICE | ||||||
| Reviewer - IEEE Transactions on Computers - IEEE Transactions on VLSI - IEEE Journal on Selected Areas of Communications - International Journal of Security and Networks - IEEE Transactions on Dependable and Secure Computing - ACM Transactions on Embedded Computing Systems - IEEE/ACM International Symp. On Microarchitecture (MICRO) - ACM FPGA - EURASIP JES - IEEE Field Programmable Logic - IEEE International Symposium on Circuits and Systems - International Journal on Computer Languages, Systems, and Structures - SPIE Journal of Electronic Imaging Session Chair - Globecomm 2005 Membership - IEEE (EE) and ACM since 1999 |
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| PROJECTS | ||||||
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• XCXT : Crystal Compensated Crystal Based Timer |
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| PUBLICATIONS | ||||||
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Jonathan Friedman,
Zainul M Charbiwala,
Thomas Schmid,
Young H Cho,
Mani B Srivastava,
"Angle-of-Arrival Assisted Radio Inteferometry (ARI) Target Localization,"
Proceedings of MILCOM 2008 [Accepted]
,
November 2008.
(TR-UCLA-NESL-200808-04)
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Thomas Schmid,
Jonathan Friedman,
Zainul M Charbiwala,
Young H Cho,
Mani B Srivastava,
"Low-Power High-Accuracy Timing Systems for Efficient Duty Cycling,"
ISLPED 2008
,
August 2008.
(TR-UCLA-NESL-200805-01)
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Thomas Schmid,
Zainul M Charbiwala,
Jonathan Friedman,
Young H Cho,
Mani B Srivastava,
"Exploiting Manufacturing Variations for Compensating Environment-induced Clock Drift in Time Synchronization,"
ACM Sigmetrics 2008
,
June 2008.
(TR-UCLA-NESL-200802-01)
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Thomas Schmid,
Jonathan Friedman,
Zainul M Charbiwala,
Young H Cho,
Mani B Srivastava,
"XCXO: An Ultra-low Cost Ultra-high Accuracy Clock System for Wireless Sensor Networks in Harsh Remote Outdoor Environments,"
ISSCC/DAC 2008 (Unpublished Student Design Contest Entry, Award Winner)
,
February 2008.
(TR-UCLA-NESL-200802-02)
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| OTHER PUBLICATIONS | ||||||
| Book Chapter B1. Young H. Cho, "Automatic Target Recognition Application using Field Programmable Gate Array," pending publication as part of Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation by Scott Hauck and Andre Dehon. Papers Submitted for Review and Papers in Preparation R1. James Moscola, Phillip H. Jones, Young H. Cho, and John W. Lockwood, "Parallel Hardware Architecture for RNA Covariance Model Parser." in preparation for The 14th International Symposium on High-Performance Computer Architecture (HPCA'08).
R2. Phillip H. Jones, R3. Phillip H. Jones, Young H. Cho, and John W. Lockwood, "Adaptive Designs with Thermal Feedback in Reconfigurable Hardware." submitted to IEEE Transactions on Computers. R4. Young H. Cho and William H. Mangione-Smith, "High-performance String Search for Network Security using Random-Access-Memories." in preparation for resubmission to IEEE Transactions on VLSI Systems (IEEE TVLSI). Refereed Journal Publications J1. Young H. Cho and William H. Mangione-Smith, "Deep Network Packet Filter Design for Reconfigurable Devices." ACM Transactions on Embedded Computing Systems (ACM TECS), 2007. J2. James. Moscola, Young H. Cho, and John W. Lockwood, "High Performance Grammar Parsing Hardware for Network Packet Payload Processing." Special issue of ACM Transaction on Design Automation of Electronic Systems on "Demonstrable Software Systems and Hardware Platforms" (ACM TODAES), 2007. Refereed Conference Publications C1. Phillip H. Jones, James Moscola, Young H. Cho, and John W. Lockwood, "Adaptive Thermoregulation for Applications on Reconfigurable Devices." 17th IEEE International Conference on Field Programmable Logic and Applications (FPL), Amsterdam, Netherlands, August 27-29, 2007 (~21% acceptance rate). C2. Moshe Looks, Ronald P. Loui, John W. Lockwood, Adam Covington, Andrew Levine, Young H. Cho, "Streaming Hierarchical Clustering for Text Mining." IEEE Aerospace Conference, Big Sky, MT, March 3-10, 2007. C3. Andrew Levine, Ronald P. Loui, John W. Lockwood, Young H. Cho, "Sensitivity Analysis of Gigabit Concept Mining System." IEEE Aerospace Conference, Big Sky, MT, March 3-10, 2007. C4. James Moscola, Young H. Cho, and John W. Lockwood, "Hardware-Accelerated Parser for Extraction of Metadata In Semantic Network Content." IEEE Aerospace Conference, Big Sky, MT, March 3-10, 2007. C5. Phillip H. Jones, Young H. Cho, and John W. Lockwood, "Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads." 20th IEEE/ACM International Conference on VLSI Design, Bangalore, India, January 6-10, 2007 [Best Paper of VLSI Design Conference]. C6. Phillip H. Jones, Young H. Cho, and John W. Lockwood, "An Adaptive Frequency Control Method using Thermal Feedback for Reconfigurable Hardware Applications." IEEE International Conference on Field Programmable Technology (FPT), Bangkok, Thailand, December 13-15, 2006. C7. James M. Moscola, Young H. Cho, and John W. Lockwood, "A Reconfigurable Architecture for Multi-gigabit-Speed Content-based Routing." 14th IEEE Hot Interconnects, Stanford, CA August 23-25, 2006. C8. G. Adam Covington, Charles L.G. Comstock, Andrew A. Levine, John W. Lockwood, Young H. Cho, "High Speed Document Clustering in Reconfigurable Hardware." 16th IEEE International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 2006. (~27% acceptance rate) C9. Phillip H. Jones, John W. Lockwood, and Young H. Cho, "A Thermal Management and Profiling Method for Reconfigurable Hardware Applications." 16th IEEE International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 2006. (~27% acceptance rate) C10. Young H. Cho, James M. Moscola, and John W. Lockwood, "Context-Free Grammar based Token Tagger in Reconfigurable Devices." IEEE ICDE - International Workshop on Semantics enabled Networks and Services (ICDE SeNS), April 3-7, Atlanta, GA, 2006.
C11. Young H. Cho and William H. Mangione-Smith, "High Performance Context Free Grammar Parser for
Network Intrusion Detection."
Advanced Networking and Communications Hardware Workshop
(ANCHOR),
C12. Young H. Cho and William H. Mangione-Smith, "A Pattern Matching Co-processor
for Network Security." 42nd IEEE/ACM Design Automation Conference,
C13. Young H. Cho and William H. Mangione-Smith, "Fast reconfiguring
Deep Packet Filter for 1+ Gigabit Network."
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM),
C14. Young H. Cho and William H. Mangione-Smith, "Programmable Hardware
for Deep Packet Filtering on a Large Signature Set." First
Watson Conference on Interaction between Architecture, Circuits, and Compilers(P=ac2),
C15. Young H. Cho and William H. Mangione-Smith, "Deep Packet Filter
with Dedicated Logic and Read-Only-Memories." IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM),
C16. Young H. Cho and William H. Mangione-Smith, "Specialized Hardware
for Deep Network Packet Filtering." International Conference on Field Programmable Logic and Applications
(FPL),
C17. Young H. Cho, David Brunke, Greg Allen, and Brian Evans, "Optimization of Vertical and Horizontal Beamforming Kernels on the PowerPC G4
Processor with AltiVec Technology." 34th
IEEE Asilomar Conference on Signals, Systems, and Computers,
C18.
Young H. Cho, "Optimized Automatic
Target Recognition Algorithm on
Scalable Myrinet/Field Programmable Array Nodes." 34th
IEEE Asilomar Conference on Signals, Systems, and Computers,
C19. Ruth Sivilotti, Young H. Cho, Wen-King Su, Danny Cohen, and Brian
Bray, "Scalable Network Based FPGA Accelerators for an Automatic Target
Recognition Application." IEEE Symposium
on Field-Programmable Custom Computing Machines (FCCM), Refereed Posters O1. Phillip H. Jones, James Moscola, Young H. Cho, and John W. Lockwood, "Changing Output Quality for Thermal Management." IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa Valley, CA, April 2007. O2. James Moscola, Young H. Cho, and John W. Lockwood, "Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices." IEEE 16th International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 2006. O3. James Moscola, Young H. Cho, and John W. Lockwood, "Content-Free Grammar Parsing for High-Speed Network Applications in Reconfigurable Hardware." 9th SIGDA Ph.D. Forum at DAC 2006, San Francisco, CA, July 25, 2006. O4. James M. Moscola, Young H. Cho, and John W. Lockwood, "A Scalable Hybrid Regular Expression Pattern Matcher." IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa Valley, CA, April 2006. O5. Arpith C. Jacob, Brandon Harris, Jeremy Buhler, Roger Chamberlain, and Young H. Cho, "Scalable Softcore Vector Processor for Biosequence Applications." IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa Valley, CA, April 2006. O6. Shobana Padmanabhan, Moshe Looks, Dan Legorreta, Young Cho, and John W. Lockwood, "A Hardware Implementation of Hierarchical Clustering." IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa Valley, CA, April 2006. O7. James M. Moscola, Young H. Cho, and John W. Lockwood, "Reconfigurable Context-Free Grammar based Data Processing Hardware with Error Recovery." 13th IEEE Reconfigurable Architectures Workshop (RAW), Rhodes Island, Greece, April 2006. O8. Young H. Cho, James M. Moscola, and John W. Lockwood, "Context-Free Grammar based Token Tagger in Reconfigurable Devices." 14th ACM/SIGDA International Symposium on Field-Programmable Gate Array (FPGA), Monterey, CA, February 2006. Non-Refereed Publications N1. Wen-King Su, Young H. Cho, Ruth Sivilotti, and Danny Cohen "Scalable, Network-Connected, Reconfigurable, Hardware Accelerators for an Automatic-Target-Recognition Application." Tech Report, Defense Advanced Research Projects Agency, May 1998. N2. Wen-King Su, Young H. Cho, Ruth Sivilotti, Danny Cohen, and Brian K. Bray, "Myricom's FPGA based Approach to ATR/SLD." ARPA/ACS-PI-Meeting Presentation, November 1997. N3. Phillip H. Jones, Young H. Cho, and John W. Lockwood, "Adaptive Control of FPGA Computation with Thermal Feedback." The Syndicated, Q4, 2006.
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| PATENTS | ||||||
| 1 "HIGH-PERFORMANCE CONTEXT-FREE GRAMMAR PARSER FOR POLYMORPHIC MALWARE DETECTION," International Patent No. WO2006113722, Published on October 26, 2006, Inventors: Young H. Cho and William Mangione-Smith, Applicant: University of California. 2 "METHOD AND APPARATUS FOR DEEP PACKET INSPECTION," International Patent No. WO2006031496, Published on March 23, 2006, Inventors: Young H. Cho and William Mangione-Smith, Applicant: University of California. 3 "PROGRAMMABLE HARDWARE FOR DEEP PACKET FILTERING," International Patent No. WO2005104443, EP1738531, Published on November 3, 2005, Inventors: Young H. Cho and William Mangione-Smith, Applicant: University of California. |
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| AWARDS AND HONORS | ||||||
| - Outstanding CS152 (Undergraduate Computer Architecture) Teaching Assistant Award - 1996 - Altera University Award Scholarship - 2000 - John Deere Scholarship - 2003 |
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| SKILLS | ||||||
| Operating Systems: Various UNIX based systems (Linux, BSD, Solaris, AIX, and etc.), Windows based Systems, and Berkeley Mote Sensor node (TinyOS) Hardware Platforms: Field Programmable Gate Arrays (Xilinx, Altera, and ORCA/Lucent) Hardware Tools: Cadence ASIC Design Tools, Xilinx ISE, Altera Quartus, and Modelsim Development Languages: VHDL, Verilog, AHDL, C, C++, Java, Basic, Pascal, Visual C++ |
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| PERSONAL WEBSITE | ||||||
| http://nesl.ee.ucla.edu | ||||||
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University of California, Los Angeles
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